1. Field of the Invention
The present invention relates to computing system memories, and more particularly to structure for entering horizontal and vertical information into a two-dimensional memory array which is composed of a collection of memory chips.
2. Description of the Prior Art
A number of references exist in the prior art directed to computer memories and techniques for entering and removing data from such memories. For purposes of background, the following prior art patents are noted.
U.S. Pat. No. 3,466,611 issued Sept. 9, 1969 to A. Weinberger, entitled "Multi-Word Multi-Directional Random Access Memory System" discloses a computer memory configuration wherein multi-word access within the memory is possible in a plurality of directions.
U.S. Pat. No. 4,195,342 issued March 25, 1980 to Joyce et al., entitled "Multi-Configurable Cache Store System" describes a configuration wherein interleaving main memory modules permit the cache memory unit to perform contiguous read requests for adjacent words in main memory without waiting for the first word to be delivered before requesting the second word. This is possible with main memory modules when the adjacent locations reside in separate modules. This is accomplished by having all even addresses reside within one or more memory modules and all odd addresses within an equal number of modules.
U.S. Pat. No. 4,296,467 issued Oct. 20, 1981 to Nibby, Jr. et al. describes a rotating chip selection technique in memory subsystem which includes at least one up to a number of memory module boards identical in layout and construction. The board includes a number of memory chips which are positioned at an initial physical row location providing a predetermined number of addressable contiguous memory locations corresponding to a predetermined increment of memory capacity. The board further includes a register for receiving address signals for accessing the contents of a memory location, rotating chip selection circuits which include a set of switches and an arithmetic unit having first and second sets of input terminals. The first set of input terminals is connected to the register for receiving predetermined ones of the address signals representative of the physical row location of chips being addressed and the second set of input terminals are connected to receive signals from the set of switches. The arithmetic unit operates to perform a predetermined arithmetic operation upon the signals applied to the sets of input terminals to generate a set of logical row address signals for enabling the number of chips at the initial row location.
None of the references shows the mapping technique and hardware of the present invention.
Other references in this technical area are as follows:
______________________________________ U.S. Pat. No. ______________________________________ 3,292,151 4,025,901 3,588,829 4,126,897 3,737,866 4,128,873 4,020,470 4,309,755 4,024,508 ______________________________________